Monolithic ICs generally comprise a number of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated over a planar substrate, such as a silicon wafer. While Moore's Law has held true for decades within the IC industry, lateral scaling of IC dimensions is becoming more difficult with MOSFET gate dimensions now below 20 nm. As device sizes continue to decrease, there will come a point where it becomes impractical to continue standard planar scaling. This inflection point could be due to economics or physics, such as prohibitively high capacitance, or quantum-based variability. Stacking of transistors in a third dimension, typically referred to as vertical scaling, or 3D integration, is therefore a promising path toward greater transistor density.
While 3D integration may be achieved at a package level, for example by stacking separately manufactured chips, a monolithic 3D approach offers the greatest inter layer interconnect density, allowing 3D circuits to be constructed at the lowest level and the tightest circuit density. Generally, monolithic 3D ICs entail two or more levels of transistors that are sequentially fabricated and interconnected over a substrate. For example, beginning with a first semiconductor substrate, a first level of transistors is fabricated with conventional techniques. A donor substrate is then bonded to the first substrate and a portion of the donor substrate is cleaved off to leave a semiconductor thin film over the first level of transistors. This method is of course only one of many ways to obtain a single crystal substrate for the second layer of devices. A second level of transistors is then fabricated in the semiconductor thin film and inter-level interconnects formed between the transistor levels. Although greater alignment between transistor levels is possible with monolithic 3D ICs, the architecture of the inter-level interconnect is important in achieving a good economy of scale where the planar footprint of the monolithic 3D IC decreases proportionally with the number of transistor levels.